Browse Prior Art Database

Page Mode Operation of Dynamic Graphics Memory

IP.com Disclosure Number: IPCOM000044376D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+3]

Abstract

A technique is described whereby a video system, operating in page mode, provides an increase in data bus bandwidth without increasing the size of the data bus. A dual-port memory structure is accessed in synchronism with character tracing cycles of a cathode ray tube (CRT) to provide multiplexed accesses of the CRT and central processing unit (CPU). The dual-port memory structure allows two character clock cycles to coincide with two memory access cycles; one to read character dot information to the CRT controller (CRTC) and the other to provide accessibility to the CPU. In order to display 256 different characters with 16 background colors, eight foreground colors along with blinking attribute at each alphanumeric character, 16 bits of data are required each character clock time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 56% of the total text.

Page 1 of 2

Page Mode Operation of Dynamic Graphics Memory

A technique is described whereby a video system, operating in page mode, provides an increase in data bus bandwidth without increasing the size of the data bus. A dual-port memory structure is accessed in synchronism with character tracing cycles of a cathode ray tube (CRT) to provide multiplexed accesses of the CRT and central processing unit (CPU). The dual-port memory structure allows two character clock cycles to coincide with two memory access cycles; one to read character dot information to the CRT controller (CRTC) and the other to provide accessibility to the CPU. In order to display 256 different characters with 16 background colors, eight foreground colors along with blinking attribute at each alphanumeric character, 16 bits of data are required each character clock time. Each character block consists of eight dots requiring 139 nsec. per dot. Each character clock cycle is divided into two memory cycles, one for the CRTC and the other for the CPU. The CRTC requires 560 nsec. to fetch information from the video memory consisting of two banks of byte-wide memory. To eliminate the need for two banks of byte-wide memory, page mode dynamic memory read cycles are combined with normal read/write cycles into a single bank of dynamic memory. Page mode operation then transfers data into and out of multiple column locations of the same row selection, as shown in Fig. 1. A row address strobe (RAS) and column address st...