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Double-Polysilicon High-Capacitance DRAM Cell

IP.com Disclosure Number: IPCOM000044379D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Lu, NC: AUTHOR [+2]

Abstract

The present disclosure is directed to a new double-polysilicon high- capacitance DRAM (dynamic random-access memory) cell, which uses a first polysilicon layer as the MOS (metal oxide semiconductor) gate and a second polysilicon layer as the storage capacitor counter-electrode. There are several advantages over the conventional double-polysilicon DRAM cell structure. The cross section of this new DRAM cell is seen in Fig. 1 together with its schematic circuit diagram. C1 is the storage capacitance using the nitride/oxide composite insulator, and Cj is the storage node junction capacitance. Arrangement of two polysilicon layers 2,4 is different from that of the conventional double-polysilicon cell structure.

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Double-Polysilicon High-Capacitance DRAM Cell

The present disclosure is directed to a new double-polysilicon high- capacitance DRAM (dynamic random-access memory) cell, which uses a first polysilicon layer as the MOS (metal oxide semiconductor) gate and a second polysilicon layer as the storage capacitor counter-electrode. There are several advantages over the conventional double-polysilicon DRAM cell structure. The cross section of this new DRAM cell is seen in Fig. 1 together with its schematic circuit diagram. C1 is the storage capacitance using the nitride/oxide composite insulator, and Cj is the storage node junction capacitance. Arrangement of two polysilicon layers 2,4 is different from that of the conventional double-polysilicon cell structure. In this new cell, the first polysilicon (or polycide) layer 2 is used as MOS gate material, and the second polysilicon layer 4 overlapping on top of the first polysilicon 2 is used as a capacitor counter-electrode. Sidewall spacer 6 of the MOS gate allows realization of the lightly- doped drain (LDD) MOS transistor and also provides a smooth step coverage for the second layer polysilicon. The shallow N+ layer 8 in the Hi-C (high capacitance) region is used as both the storage electrode and source of the access transistor to facilitate the charge transfer. Since the P+ layer 10 in the Hi-C region is self- aligned to the outside edge of the spacer and is covered by the top polysilicon counter-electrode 4, the Hi-C capacitance is fully utilized without any loss due to misalignment tolerance. The nitride film 12 in the storage region can also be used as an etch stop layer for either forming the spacer or opening a borderless contact window (the borderless contact can reduce the cell area). The memory operation is the same as in the conventional double-polysilicon DRAM cell. The fabrication procedures for this double-polysilicon DRAM cell are as follows (the specific numbers quoted are for the purpose of example): 1. Grow ROX 1 (include field implant 3). 2. Grow 25 nm thin gate oxide 5 and implant the channel to adjust the threshold voltage. 3. Deposit the first layer polysilicon or polycide (e.g., poly-Si, WSi2 and Si). 4. Grow or deposit SiO2 layer 7. The thickness of the stacked layers of the gate should be larger than 500 nm to insure the spacer having suitable width to tolerate the lateral diffusion of the Hi-C p+ implanted dopants. 5. RIE (reactive ion etch) to define the MOS gate (the window opening can be down to the silicon surface or leave 10 nm of SiO2). 6. Implant arsenic to form the lightly-doped region for the LDD MOST and the n+ electrode for the Hi-C storage capacitor. In order to optimize the doping level and profile for each, the implant can be divided into two separate steps, requiring one more non-critical mask. 7. If oxide was totally removed in step 5, grow 5 nm oxide 9; if 10 nm oxide remained, remove it after the implant of step 6 and regrow 5 nm oxide 9. 8. Depos...