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Browse Prior Art Database

Self-Stress Pattern Generator

IP.com Disclosure Number: IPCOM000044397D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Coene, B: AUTHOR

Abstract

In order to accelerate the failure mechanism on a logic product when performing burn-in and life tests, the component is put in a chamber: - at elevated temperature (above temperature use conditions), - the power supplies are set above their worst-case values, and - the inputs receive a stream of data 1010101011 from pulse generators. The purpose of applying data 1010110 on the primary inputs of the component is to have the internal circuits which switch ON/OFF to accelerate the component failure modes. This technique needs an expensive electronic system, such as pulse generators and drivers, to provide the data on the inputs. The purpose of the present method is to use the component itself to supply the stream of data. This method can be applied on any logic product which is an LSSD (Level Sensitive Scan Design).

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Self-Stress Pattern Generator

In order to accelerate the failure mechanism on a logic product when performing burn-in and life tests, the component is put in a chamber: - at elevated temperature (above temperature use conditions), - the power supplies are set above their worst-case values, and - the inputs receive a stream of data 1010101011 from pulse generators. The purpose of applying data 1010110 on the primary inputs of the component is to have the internal circuits which switch ON/OFF to accelerate the component failure modes. This technique needs an expensive electronic system, such as pulse generators and drivers, to provide the data on the inputs. The purpose of the present method is to use the component itself to supply the stream of data. This method can be applied on any logic product which is an LSSD (Level Sensitive Scan Design). Mode of operation (with reference to the figure): -the input and output of each SRL (Shift Register Latch) are connected together in order to make a ring oscillator. An inverter between the input and output might be needed to have a correct phase. - each SRL is set in a flush mode: "A" and "B" clock active, "C" clock inactive. -in order to have a maximum of circuits which switch in the component, the primary inputs of the chip might be tied to the output of the SRL. -if several SRLs are present on the chip, each SRL is set as a ring oscillator. The reason for connecting the SRL as a ring oscillator is to provide a pulse gen...