Browse Prior Art Database

Latch Mapping for a Logic Transformation System

IP.com Disclosure Number: IPCOM000044402D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

DasGupta, S: AUTHOR [+3]

Abstract

This process for mapping a design from one technology to another maps latches in a way that preserves the logical requirements of the original design and satisfies the electrical constraints of the new technology as well as any new performance requirements that the designer sees fit to impose. The first step is to extract structural and logical data relating to latches from both the source and target technologies and then create a matrix (hopefully, sparse) that defines suitable mapping choices for each source latch. User-defined control information helps to define the preferred order to mapping choices in cases of similar fits. The next step is to collect application-oriented data regarding each specific source latch that is being remapped.

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Latch Mapping for a Logic Transformation System

This process for mapping a design from one technology to another maps latches in a way that preserves the logical requirements of the original design and satisfies the electrical constraints of the new technology as well as any new performance requirements that the designer sees fit to impose. The first step is to extract structural and logical data relating to latches from both the source and target technologies and then create a matrix (hopefully, sparse) that defines suitable mapping choices for each source latch. User-defined control information helps to define the preferred order to mapping choices in cases of similar fits. The next step is to collect application-oriented data regarding each specific source latch that is being remapped. This is the data that is needed to customize a particular target latch offering satisfy the design requirement. Most, if not all, of this data is logical in nature since electrical considerations in the source technology bear little or no significance in the target technology due to their dissimilarities. Given the information just collected, checks are made to determine if the source latches can be mapped into the target technology. An example of this is the existence of latches with DC resets in the source design that needs to be mapped into a technology that offers no latch that has either a DC set or reset. Clearly, such a mapping is impossible and so should not be allowed to proceed any further. As a final step before general optimizati...