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Chip Select Circuit for Multi-Chip RAM Modules

IP.com Disclosure Number: IPCOM000044404D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 71K

Publishing Venue

IBM

Related People

Fitzgerald, BF: AUTHOR [+4]

Abstract

A chip select circuit for a multi-chip RAM (random-access memory) module reduces the number of module pins required to address all the chips in a module, with each additional doubling of the memory bits requiring only one additional select line. This method describes the chip select circuits used in a module that can contain up to eight chips (Fig. 1). The chip decoding that used to be done on memory cards is done within each chip. The addressing of the chips is done using binary chip address lines, analogous to word and bit address lines. The module is thus addressed as though it contained one large chip. The chip addresses are input to the module followed by a single module enable input. Each chip is programmed to start for one unique chip address by additional hardwired chip input pads, called program pads (PP).

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Chip Select Circuit for Multi-Chip RAM Modules

A chip select circuit for a multi-chip RAM (random-access memory) module reduces the number of module pins required to address all the chips in a module, with each additional doubling of the memory bits requiring only one additional select line. This method describes the chip select circuits used in a module that can contain up to eight chips (Fig. 1). The chip decoding that used to be done on memory cards is done within each chip. The addressing of the chips is done using binary chip address lines, analogous to word and bit address lines. The module is thus addressed as though it contained one large chip. The chip addresses are input to the module followed by a single module enable input. Each chip is programmed to start for one unique chip address by additional hardwired chip input pads, called program pads (PP). Each chip has compare circuits to compare the incoming chip address with the voltage state of its program pads. When a compare is made, the chip functions fully for a read or write cycle. When a compare is not made, the chip returns to the standby state. This eight-chip module is made of two four-chip decks and is wired such that either one or two of the eight chips can be selected for read and write. If one chip is selected, the data I/O bus connected to that chip is used. If two chips are selected, both data I/O busses are used in parallel. The 9/18 module pin selects one- or two-chip operation. When the 9/18 input is at ground, all eight chips have different voltages on PP1, PP2 and PP3. Thus, it is possible to select one out of eight chips. When the 9/18 input is at VH, chips 1 and 2...