Browse Prior Art Database

Improved Cache to Instruction Buffer System Organization

IP.com Disclosure Number: IPCOM000044406D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Capozzi, AJ: AUTHOR [+3]

Abstract

An improved cache to buffer system can be organized by utilizing an intermediate buffer as the source of the instruction stream. This system obtains the benefits of an I-cache/D-cache organization without implementing the I-cache. To fully exploit the intermediate buffer 11 to instruction buffer (I-buffer) 12 implementation, it is desirable to utilize the widest possible data path available at buffer 11. Since this is a read-only path, the logic is minimal, and represents an extra load on the buffer 11 to cache 13 data path. There are many existing algorithms and de sign approaches to instruction prefetching and branch prediction. Proper selection of the implementation technique will ensure minimum interruption to the instruction stream although the buffer 11 can be expected to have a slower access time than cache 13.

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Improved Cache to Instruction Buffer System Organization

An improved cache to buffer system can be organized by utilizing an intermediate buffer as the source of the instruction stream. This system obtains the benefits of an I-cache/D-cache organization without implementing the I- cache. To fully exploit the intermediate buffer 11 to instruction buffer (I-buffer) 12 implementation, it is desirable to utilize the widest possible data path available at buffer 11. Since this is a read-only path, the logic is minimal, and represents an extra load on the buffer 11 to cache 13 data path. There are many existing algorithms and de sign approaches to instruction prefetching and branch prediction. Proper selection of the implementation technique will ensure minimum interruption to the instruction stream although the buffer 11 can be expected to have a slower access time than cache 13. That is, the slower access time will be more than offset by the decreased number of accesses from the I-buffer 12. There will also be an apparent increase in cache 13 capacity (for data) by excluding the instruction stream from that portion of the storage system. The increase in performance is job stream dependent. With this storage system, a separate, dedicated buffer is not required and the available capacity of buffer 11 would exceed the capacity generally allocated for that dedicated buffer, thereby reducing prefetch cache misses. Assuming a "store through" cache 13 design, stores into th...