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Cache Enhancement for Store Multiple Instruction

IP.com Disclosure Number: IPCOM000044408D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Capozzi, AJ: AUTHOR [+3]

Abstract

Store multiple (STM) is a commonly executed instruction which stores up to 16 General Purpose Registers (GPRs). An implementation technique is described to enhance system performance in higher performance processors by speeding up the execution of the STM instruction. The contents of the GPRs can be replicated at the Cache data register. This replication will be described with alignment on word boundaries. Although byte boundary alignment is feasible, the low frequency of occurrence may not make that design practical to implement. In any event, this discussion applies to byte, as well as word, boundary- aligned data. To facilitate discussion, a data register width of 32 bytes (i.e., 256 bits) will be considered. With word boundary alignment, this will give a replication factor of 8 for the GPRs.

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Cache Enhancement for Store Multiple Instruction

Store multiple (STM) is a commonly executed instruction which stores up to 16 General Purpose Registers (GPRs). An implementation technique is described to enhance system performance in higher performance processors by speeding up the execution of the STM instruction. The contents of the GPRs can be replicated at the Cache data register. This replication will be described with alignment on word boundaries. Although byte boundary alignment is feasible, the low frequency of occurrence may not make that design practical to implement. In any event, this discussion applies to byte, as well as word, boundary- aligned data. To facilitate discussion, a data register width of 32 bytes
(i.e., 256 bits) will be considered. With word boundary alignment, this will give a replication factor of 8 for the GPRs. The bus which loads the GPRs within the processor is extended to the cache data register chips. Each time a GPR is loaded (or altered) in the processor, the corresponding location(s) at the Cache data register will also be loaded. Referring to the figure, when a STM instruction is encountered, the starting storage address, starting GPR and the number of GPRs to be stored will be transmitted to the Cache controls 11. The Cache controls 11 will then perform the appropriate gating to effect the simultaneous transfer of the replicated GPRs 12, 13, 14, 15 to the data register 16, and the subsequent store operation. Operation would proceed in the follo...