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Browse Prior Art Database

Trap Node Sense Amplifier for Shared Wordline RAM

IP.com Disclosure Number: IPCOM000044422D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

The shared wordline (SWL) random-access memory (RAM) cell requires control of the plate lines by the sense amplifier (SA) to restore data. A compact circuit is desired so that the SA area does not detract from the SWL cell density advantage. This article provides a denser sense amplifier for SWL RAMs by reducing the device count to 12 devices and by not requiring the opposite SA node to control the plate line. Trap nodes A and B are central to the circuit operation (Fig. 1). The trap nodes can be at a voltage higher than Vdd (the up level of the gate and plate control clocks) by means of small boost capacitors 7 and 8, or the trap nodes can be discharged to ground. When the trap nodes are at their high voltage level, the associated plate line is controlled by the plate control line.

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Trap Node Sense Amplifier for Shared Wordline RAM

The shared wordline (SWL) random-access memory (RAM) cell requires control of the plate lines by the sense amplifier (SA) to restore data. A compact circuit is desired so that the SA area does not detract from the SWL cell density advantage. This article provides a denser sense amplifier for SWL RAMs by reducing the device count to 12 devices and by not requiring the opposite SA node to control the plate line. Trap nodes A and B are central to the circuit operation (Fig. 1). The trap nodes can be at a voltage higher than Vdd (the up level of the gate and plate control clocks) by means of small boost capacitors 7 and 8, or the trap nodes can be discharged to ground. When the trap nodes are at their high voltage level, the associated plate line is controlled by the plate control line. During the memory operation these trap nodes are conditionally discharged to ground by the gate 1 and gate 2 lines falling to ground. The conditional discharge depends on the state of the bit lines, and hence provides the required data information feedback for the restore operation. Note that the logic function of the circuit allows the near bit line (BL) to conditionally discharge the trap node. The circuit operation through a memory cycle is described with reference to the timing diagram (Fig. 2). At time 1, gate 2 falls to discharge trap node B, assuming cells under plate 1 are to be accessed. At time 2, before we read the cell, clock P falls to isolate the BL from the power supply voltage Vdd. The plate control line falls to discharge plate 1, preparing the cells under plate 1 for reading. At time 3, the selected WL rises to transfer the cell's signal to the BL. A dummy wordline (not shown) would also rise to access a dummy cell (not shown) on BLN. At time 4, the selected WL and dummy wordline are pulled back to ground before the sense amplifier control SL...