Browse Prior Art Database

Comparator-Based Current-Controlled Regulator Circuit

IP.com Disclosure Number: IPCOM000044424D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Bogdanski, JW: AUTHOR [+3]

Abstract

This article describes a pulse-width-controlled low voltage regulator in which the output is regulated by controlling the peak current through the power-switching transistors. The circuit utilizes a group of comparators for an inexpensive, discrete component approach, and obtains an instantaneous current-limiting, soft-starting, over-current shutdown and quick AC line loss detect and reset. In the figure, the clock signal at point A goes high, causing the power switch to come on. Current builds up in the power device until it reaches a level corresponding to the feedback reference level which results in tripping comparator gate M1-4, sending point B high enough to reset the drive signal through gate M1-2. Gate M1-3 senses the high reset signal and goes high to reenforce gate M1-4's latched state.

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Comparator-Based Current-Controlled Regulator Circuit

This article describes a pulse-width-controlled low voltage regulator in which the output is regulated by controlling the peak current through the power-switching transistors. The circuit utilizes a group of comparators for an inexpensive, discrete component approach, and obtains an instantaneous current-limiting, soft-starting, over-current shutdown and quick AC line loss detect and reset. In the figure, the clock signal at point A goes high, causing the power switch to come on. Current builds up in the power device until it reaches a level corresponding to the feedback reference level which results in tripping comparator gate M1-4, sending point B high enough to reset the drive signal through gate M1-2. Gate M1-3 senses the high reset signal and goes high to reenforce gate M1-4's latched state. Otherwise, point B would fall as the current falls. Once the clock goes low, the latch is reset but the power device remains off because a low clock overrides all other conditions. In the event of an overload on the output, the feedback reference rises to provide more power and thus hold up the output. If this reference rises above voltage VR1, comparator M2-4 trips, sending point C high, shutting off the power switch through gate M1-4 and latching itself high. This latch remains until the AC power is removed and reference voltage VR goes low. When AC power is removed, capacitor C1 discharges causing gates M2-1 and M2...