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Self-Aligned Silicon Nitride-Polyimide Double Step Via Hole

IP.com Disclosure Number: IPCOM000044428D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 56K

Publishing Venue

IBM

Related People

Alcorn, C: AUTHOR [+3]

Abstract

Composite dielectric layers have been used as passivation layers for integrated circuits in the prior art [*]. The typical composite dielectric layers include a lower layer of silicon nitride on top of which is deposited a layer of polyimide. A problem arises when such composite dielectric layers serve as the insulator layer separating a first metal interconnection layer from a second metal interconnection layer. Where a via hole is to be formed in the composite dielectric layer between the first metal layer and the second metal layer, the relative thickness of the insulator layer creates a substantially large vertical step over which the second metal layer must traverse in order to make electrical contact with the first metal layer.

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Self-Aligned Silicon Nitride-Polyimide Double Step Via Hole

Composite dielectric layers have been used as passivation layers for integrated circuits in the prior art [*]. The typical composite dielectric layers include a lower layer of silicon nitride on top of which is deposited a layer of polyimide. A problem arises when such composite dielectric layers serve as the insulator layer separating a first metal interconnection layer from a second metal interconnection layer. Where a via hole is to be formed in the composite dielectric layer between the first metal layer and the second metal layer, the relative thickness of the insulator layer creates a substantially large vertical step over which the second metal layer must traverse in order to make electrical contact with the first metal layer. This relatively large vertical step imposes a stress on the second metal layer in the via hole region, and can cause cracking and poor electrical contact. This problem is solved by the sequence of process steps described below, which provides a more gradual sequence of vertical steps in the composite dielectric layer so as to enable the second metal layer to make a more gradual descent to the lower level of the first metal layer, thereby reducing the tendency for stress cracking to take place in the via hole region. Fig. 1 illustrates a first stage in the process. A silicon substrate 2 has a silicon dioxide layer 3 thereon, upon which has been deposited a first metal layer 4 which is patterned into the desired interconnection pattern. Then a continuous layer 6 of silicon nitride followed by a continuous layer 8 of polyimide are deposited on top of the first metal layer 4. In order to pattern the via holes in the desired locations in the composite dielectric layers of polyimide 8 and silicon nitride 6, a layer of photoresist 10 is applied to the upper surface of the polyimide layer 8 and a mask hole 12 is formed in the photoresist layer 10 by conventional photolithographic techniques. Fig. 2 illustrates the next step in the process wherein the hole 12 is extended through the polyimide layer 8 by reactive ion etching with molecular oxygen. The molecular oxygen attacks both the polyimide layer 8 and, to a lesser degree, the photoresist layer 10, thereby forming the inclined sidewalls 14 in the photoresist layer 10 and the vertical sidewalls 16 in the polyimide layer 8. Since the molecular oxygen in the reactive ion etching step does not significantly attack the silicon nitride layer 6, this stage of the etching is self- limiting. Fig. 3 illustrates the nex...