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Branch Instructions for Long CODE Sequences

IP.com Disclosure Number: IPCOM000044430D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Brady, JT: AUTHOR

Abstract

This article describes a STORE CONDITION CODE IN REGISTER instruction and a TEST REGISTER UNDER MASK INSTRUCTION to support long sequences of instructions in newly written code, resulting in improved cache hit ratios and fewer lost cycles due to errors in branch guessing. In addition, code may be easier to write and debug, resulting in improved programmer productivity. The description of the instructions follows: Instruction name: STORE CONDITION CODE IN REGISTER Format: SCCR M1, M2, D3 (B3) (S FORMAT-MODIFIED) (Image Omitted) Bits 20 to 31 of the third operand's effective address are interpreted as fields M4, M5 and R6, as shown below: (Image Omitted) The contents of R6 are modified by placing the current condition code (CC) into the register R6 according to the options specified by the contents of M2, M4 and M5 (Fig.

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Branch Instructions for Long CODE Sequences

This article describes a STORE CONDITION CODE IN REGISTER instruction and a TEST REGISTER UNDER MASK INSTRUCTION to support long sequences of instructions in newly written code, resulting in improved cache hit ratios and fewer lost cycles due to errors in branch guessing. In addition, code may be easier to write and debug, resulting in improved programmer productivity. The description of the instructions follows: Instruction name: STORE CONDITION CODE IN REGISTER Format: SCCR M1, M2, D3 (B3) (S FORMAT-MODIFIED)

(Image Omitted)

Bits 20 to 31 of the third operand's effective address are interpreted as fields M4, M5 and R6, as shown below:

(Image Omitted)

The contents of R6 are modified by placing the current condition code (CC) into the register R6 according to the options specified by the contents of M2, M4 and M5 (Fig. 2) as specified below. M1 - specifies where in R6 to place the processed condition code. M1 takes on values from 0 to 7 to specify which four-bit portion of R6 is modified. M1 is three bits in length.

(Image Omitted)

M2 - specifies how the bits in the condition code are distributed into the four bits in R6, according to the following table. M2 is five bits in length.

(Image Omitted)

The above assignments are arbitrary and any equivalent mapping is usable. In this mapping the first two bits of M2 specify the condition code to store in bit 1 of R6. The second two bits specify the condition code to store in bit 2. The final bit specifies whether to store the remaining condition codes in ascending (bit 5 = 0) or descending order (bit 5 = 1). The implementation of the values of M2 depends on the difficulty of hardware implementation vs. utility.

(Image Omitted)

M4 - four bits used to determine which condition codes are to be processed. If bits 0, 1, 2, or 3 of the mask are a 1 then the respective condition code is processed. When they are 0, the resulting position selected in R6 (Fig. 2) for that condition code is unchanged. Note: This is not a fixed position within the four-bit field, but is dependent on the setting of M2. M5 - used to select the operation used to store the condition code. The following table defines those operations.

(Image Omitted)

STO - place the selected condition code (CC) bits unchanged in the selected field of R6. STO NOT - replace the selected bits in R6 with the (inverted)

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selected CC bits. AND - (logic AND) the selected CC...