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Write Masking Method for Writing a Bit of Image Information Into a Pixel

IP.com Disclosure Number: IPCOM000044434D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Aoki, Y: AUTHOR [+2]

Abstract

This article describes a method for writing a bit of image information into a pixel (picture element) (byte) in an image memory. A bit position or positions to be written within a selected pixel are specified by a mask bit register. Referring to the drawing, a bit of image information is supplied to an image memory write circuit 10 while an MPU data or mask is supplied to a mask bit register 12 through a rotator 14. The mask bit register 12 is an eight-bit register whose bit positions correspond to those of a pixel in an image memory 16. A selected pixel is written with the image information bit only where a corresponding mask bit or bits in the register 12 are on. The mask bit register 12 is normally addressed by an MPU (not shown) and then loaded with the MPU data.

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Write Masking Method for Writing a Bit of Image Information Into a Pixel

This article describes a method for writing a bit of image information into a pixel (picture element) (byte) in an image memory. A bit position or positions to be written within a selected pixel are specified by a mask bit register. Referring to the drawing, a bit of image information is supplied to an image memory write circuit 10 while an MPU data or mask is supplied to a mask bit register 12 through a rotator 14. The mask bit register 12 is an eight-bit register whose bit positions correspond to those of a pixel in an image memory 16. A selected pixel is written with the image information bit only where a corresponding mask bit or bits in the register 12 are on. The mask bit register 12 is normally addressed by an MPU (not shown) and then loaded with the MPU data. Therefore, it would have to be addressed each time a different mask is to be used. In the present method, however, such addressing is not required and the mask bit register 12 is forced to a transparent state by a transparent mode signal. In the transparent state, the mask bit register 12 unconditionally passes the MPU data toward the image memory write circuit 10, thus requiring no addressing. Such a transparent state can be realized by using polarity-hold latches for the mask bit register 12.

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