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Field Emission Tip Arrays for Fabrication of Integrated Circuits by CVD Without Lithography

IP.com Disclosure Number: IPCOM000044452D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-05
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Cuomo, JJ: AUTHOR [+3]

Abstract

Patterning of integrated circuits requires multiple cycles of lithography, CVD (chemical vapor deposition) or ion implantation and thermal annealing, as described herein. Methods of fabricating arrays of field emission tips, which may be activated in desired patterns to cause the growth of patterned structures in a CVD-type reactor, is described herein. In this way, complicated integrated circuits may be grown without lithography and without removal of the substrate from the reactor. One variant of this method combines an array of field emission tips with lateral translation by means of piezoelectric inchworms or "louse" devices known in the art 1. A preferred version of the method uses the techniques described [2] to produce an array of field emission tips on a block of graphite.

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Field Emission Tip Arrays for Fabrication of Integrated Circuits by CVD Without Lithography

Patterning of integrated circuits requires multiple cycles of lithography, CVD (chemical vapor deposition) or ion implantation and thermal annealing, as described herein. Methods of fabricating arrays of field emission tips, which may be activated in desired patterns to cause the growth of patterned structures in a CVD-type reactor, is described herein. In this way, complicated integrated circuits may be grown without lithography and without removal of the substrate from the reactor. One variant of this method combines an array of field emission tips with lateral translation by means of piezoelectric inchworms or "louse" devices known in the art 1. A preferred version of the method uses the techniques described [2] to produce an array of field emission tips on a block of graphite. Initially, lithography is used to produce an insulating film over the regions of the block where tips are not desired. Then the tips are grown, as described in [2]. Lithography is used to deposit metal lines to make contact with the array of tips and to coat the tips to improve their conductivity. A second preferred embodiment of the invention uses the art of [3] to produce a uniform array of tips across the entire surface of a graphite block. The uniform array is then trimmed to the correct pattern using an excimer laser beam (g = 193 nm) or a scanning ion beam to demolish the tips in the area w...