Browse Prior Art Database

Serial Implementation of Measuring the Weighted Syndrome Sums

IP.com Disclosure Number: IPCOM000044461D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 77K

Publishing Venue

IBM

Related People

Savir, J: AUTHOR [+2]

Abstract

The weighted syndrome sums approach to VLSI testing is applicable for self-testing, where the number of syndrome references needed to be stored in an on-chip ROS is kept minimum. A serial process and the hardware implementation of it which computes the weighted syndrome sums is described herein. Let Si, i=1,2,...,m be the syndromes of the output functions of an n input, m output macro. The weighted syndrome sums is defined as m WSS= S WiSi i=1 where Wi, i=1,2,...,m are integer weights. An easily implementable coefficient is observed to be progressive powers of 2, since they can be realized by shifting (prior to the addition step necessary for computing the WSS). Thus, for practical purposes, it is convenient to choose the coefficients Wi=2i-1, i=1,2,...,m.

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Serial Implementation of Measuring the Weighted Syndrome Sums

The weighted syndrome sums approach to VLSI testing is applicable for self- testing, where the number of syndrome references needed to be stored in an on- chip ROS is kept minimum. A serial process and the hardware implementation of it which computes the weighted syndrome sums is described herein. Let Si, i=1,2,...,m be the syndromes of the output functions of an n input, m output macro. The weighted syndrome sums is defined as m WSS= S WiSi i=1 where Wi, i=1,2,...,m are integer weights. An easily implementable coefficient is observed to be progressive powers of 2, since they can be realized by shifting (prior to the addition step necessary for computing the WSS). Thus, for practical purposes, it is convenient to choose the coefficients Wi=2i-1, i=1,2,...,m. A serial circuit that implements this measurement of the WSS is given in Fig. 1. Assume that all combinations are applied to the inputs of the macro via the input latches (ILs) implemented, for example, by modifying the SRL chain to an LFSR, and applying an the non-zero combinations. The zero combination is applied as an extra vector. Each time an input is applied, the output response is latched at the output latches (OLs). The measurement circuitry starts off with a cleared shift register (ML). After the output vector has been latched in the OLs, this bit pattern is scanned out one bit at a time, and the full adder (FA) adds the current value of ML1, with the incoming bit, the previous carry stored in the CL latch from the previous cycle, and updates the value of ML, producing also a carry to be processed with the next incoming bit in the next cycle. Next, the contents of the shift register, ML1, is rotated...