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Half Voltage Dummy Cell

IP.com Disclosure Number: IPCOM000044466D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 65K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

This article describes a half voltage dummy cell which is identical in layout to the normal cell except that it uses the plate voltage to generate a stored charge level in the dummy cell halfway between a zero and a one state. This technique can be used with memory cells that have stored voltages of 2VDD-VT for a logical one and VDD-VT for a logical zero, such as the shared word line memory cell * . The dummy cell write operation begins with a voltage of VDD on plate line 11 of dummy cell 12. Since no word line is turned on along the bit line 13 that connects to dummy cell 12, plate line 11 is shared with the normal cells. The dummy word line (DWL) 14 would fall to ground, after the fill/spill action of the bit line, to isolate a VDD- VT level in the dummy cell.

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Half Voltage Dummy Cell

This article describes a half voltage dummy cell which is identical in layout to the normal cell except that it uses the plate voltage to generate a stored charge level in the dummy cell halfway between a zero and a one state. This technique can be used with memory cells that have stored voltages of 2VDD-VT for a logical one and VDD-VT for a logical zero, such as the shared word line memory cell * . The dummy cell write operation begins with a voltage of VDD on plate line 11 of dummy cell 12. Since no word line is turned on along the bit line 13 that connects to dummy cell 12, plate line 11 is shared with the normal cells. The dummy word line (DWL) 14 would fall to ground, after the fill/spill action of the bit line, to isolate a VDD- VT level in the dummy cell. Later, the plate line 11 is restored to VDD which couples the dummy cell voltage to ~ 11/4 VDD-VT, a level halfway between a one @ ~ 2VDD-VT and a zero @ VDD-VT. Fig. 2 shows the pulses of the timing diagram. Many different methods could be used to drive the plates to 1/4 VDD voltage. For example, the half voltage for the plate lines could conveniently be generated by shorting the bit lines together through a common bus which is also used for precharging the bit lines. This common bus would be held at 1/4 VDD by a bias generator circuit during the time that the plates were being driven to 1/4 VDD. Turning on devices between the bit lines and the plate lines on the dummy cell side o...