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Optimizing Overlay in Multilevel Optical Lithography

IP.com Disclosure Number: IPCOM000044471D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Herd, H: AUTHOR [+2]

Abstract

The presented process provides optical alignment patterns on zero-level silicon wafers used in manufacturing integrated circuit chips. The zero-level patterns are used for subsequent photolithographic processing instead of conventional level-to-level alignment marks. Construction of integrated circuit chip patterns on silicon wafers requires precisely aligned vertical structures containing intricately patterned multiple layers. To reproducibly achieve layer-to-layer optical registration, two requirements must be satisfied: (1) creation and preservation of high optical contrast alignment marks and (2) a means of referencing, calibrating, and correcting for hot-process induced wafer dimensional changes. The following process achieves these goals: 1.

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Optimizing Overlay in Multilevel Optical Lithography

The presented process provides optical alignment patterns on zero-level silicon wafers used in manufacturing integrated circuit chips. The zero-level patterns are used for subsequent photolithographic processing instead of conventional level-to-level alignment marks. Construction of integrated circuit chip patterns on silicon wafers requires precisely aligned vertical structures containing intricately patterned multiple layers. To reproducibly achieve layer-to-layer optical registration, two requirements must be satisfied: (1) creation and preservation of high optical contrast alignment marks and (2) a means of referencing, calibrating, and correcting for hot-process induced wafer dimensional changes. The following process achieves these goals: 1. A zero-level mask is generated containing alignment marks and a sequence of symmetrically distributed optical verniers for analysis of overlay errors caused by wafer warpage or camera variation. 2. This mask is used to pattern a zero-level SiO2 surfaced silicon wafer by known photoresist process steps. 3. The wafer is moderately deep etched and may be conformally covered with a thin silicon nitride film. This film inhibits oxidation of the etched features during future process steps. This process has the following advantages: 1. Adequate optical contrast for either manual or automatic alignment is guaranteed. 2. The zero-level creates a standardized recording blank on...