Browse Prior Art Database

High Speed Communications Controller With Automatic Control Byte Monitor

IP.com Disclosure Number: IPCOM000044504D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Davis, GT: AUTHOR [+3]

Abstract

A technique is described whereby a controller is used to automatically monitor incoming data from a communications channel to detect control bytes in the data stream. Since the central processing unit (CPU) in a communications system is required to check each byte of incoming data received from every channel and to provide the appropriate branching instructions, if required, the controller described herein is designed to relieve the CPU of this time consuming monitoring, thus enabling the CPU to perform other functions during the monitoring phase. The block diagram of Fig. 1 shows the high speed communications controller, with automatic control byte monitoring capability, and how it monitors each byte received.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

High Speed Communications Controller With Automatic Control Byte Monitor

A technique is described whereby a controller is used to automatically monitor incoming data from a communications channel to detect control bytes in the data stream. Since the central processing unit (CPU) in a communications system is required to check each byte of incoming data received from every channel and to provide the appropriate branching instructions, if required, the controller described herein is designed to relieve the CPU of this time consuming monitoring, thus enabling the CPU to perform other functions during the monitoring phase. The block diagram of Fig. 1 shows the high speed communications controller, with automatic control byte monitoring capability, and how it monitors each byte received. Data transfers from the programmable communications interface (PCI) units 2-5 are under control of the direct memory access (DMA) controller 6, which transfers data to the main storage memory 17. A flag random-access memory (RAM) unit 13 is addressed by the data through buffer 10 and the DMA channel, encoded by logic unit 11, both enabled by AND gate 8 which is conditioned by a write (WR) pulse to strobe the flag RAM 13 only while data is valid on bus 19. Low-order addresses control an 8:1 multiplexer 14, enabling a byte-wide memory module to be used in updating the flag map. This permits the programmability of the set of flags used in each application. A different set of flags may be stored for each line, since the line number makes up part of the address. When updating flag RAM 13, data from microprocessor 1 is sent on data bus 19 through buffer 9, under the control of a chip select (C.S.) flag, while the addresses are propagated from bus 18 through buffer 12. If a logic "...