Browse Prior Art Database

Self-Aligning Metal Land and Feed-Through Structure

IP.com Disclosure Number: IPCOM000044505D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Havas, J: AUTHOR [+4]

Abstract

The number of usable circuits on semiconductor chips is generally limited by the spacing of the wiring channels. One such limiting factor is the alignment of the via hole or via stud to the metal land. This article describes a method for simultaneously forming a metal land/via stud structure which is self-aligning. Step 1: Blanket deposit CrAlCu, or any desired metal, over the entire wafer, after PtSi contacts are formed as usual, to a thickness equal to the total desired thickness of the metal lines and the stud, e.g., 2.5 microns. Step 2: Deposit a suitable masking layer, e.g., Si3N4 (or MgO, etc.) over the metal to the desired thickness, e.g., 0.75 - 1.0 micron. Step 3: Apply photoresist (P/R), expose and develop the desired metal pattern and use it as a mask to reactive ion etch (RIE) the exposed layer of Si3N4, e.g.

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Self-Aligning Metal Land and Feed-Through Structure

The number of usable circuits on semiconductor chips is generally limited by the spacing of the wiring channels. One such limiting factor is the alignment of the via hole or via stud to the metal land. This article describes a method for simultaneously forming a metal land/via stud structure which is self-aligning. Step 1: Blanket deposit CrAlCu, or any desired metal, over the entire wafer, after PtSi contacts are formed as usual, to a thickness equal to the total desired thickness of the metal lines and the stud, e.g., 2.5 microns. Step 2: Deposit a suitable masking layer, e.g., Si3N4 (or MgO, etc.) over the metal to the desired thickness, e.g., 0.75 - 1.0 micron. Step 3: Apply photoresist (P/R), expose and develop the desired metal pattern and use it as a mask to reactive ion etch (RIE) the exposed layer of Si3N4, e.g., by using CF4 . Step 4: RIE the exposed AlCu, using, for example, CCl4 or SiCl4, to a depth of, say, 1.5 microns. Note: A thin layer of Cr or any other suitable metal may be buried at this depth during step 1 for end- point detection during the RIE. Otherwise, a polysilicon wafer may be used as a monitor, the etch-rate ratio between the metal and poly-Si being previously determined (Fig. 1). Step 5: Strip the old photoresist and apply a new layer, expose and develop to retain the photoresist only where the via studs are needed. Step 6: RIE to remove the exposed Si3N4 layer. Step 7: Strip the pho...