Browse Prior Art Database

Process for Fabricating an LDDFET

IP.com Disclosure Number: IPCOM000044507D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

This article describes a simplified method of constructing a lightly doped drain/source field-effect transistor (LDDFET). The method is as follows: - Beginning with P substrate 2 (Fig. 1), form field oxide 4, typically 1 mm thick. If necessary, a channel stopper P region may be formed beneath the field oxide. Form about a 300 A gate oxide 6, then deposit N+ doped polysilicon 8 of about 5000 A thickness. Form a layer of photoresist 10 above poly 8. Then, preferably using the technique of "image transfer" or "multilayer resist," form patterns in resist 10. Employing reactive ion etching (RIE), etch poly 8 with resist 10 as the mask. The structure at this stage is illustrated in Fig. 1 Resist 10 remains in place (at least about 4000 A after RIE), and is not stripped at this stage.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 87% of the total text.

Page 1 of 2

Process for Fabricating an LDDFET

This article describes a simplified method of constructing a lightly doped drain/source field-effect transistor (LDDFET). The method is as follows: - Beginning with P substrate 2 (Fig. 1), form field oxide 4, typically 1 mm thick. If necessary, a channel stopper P region may be formed beneath the field oxide. Form about a 300 A gate oxide 6, then deposit N+ doped polysilicon 8 of about 5000 A thickness. Form a layer of photoresist 10 above poly 8. Then, preferably using the technique of "image transfer" or "multilayer resist," form patterns in resist 10. Employing reactive ion etching (RIE), etch poly 8 with resist 10 as the mask. The structure at this stage is illustrated in Fig. 1 Resist 10 remains in place (at least about 4000 A after RIE), and is not stripped at this stage. - Introduce N+ impurity 14 at the surface of the P substrate 2 through ion implantation (Fig. 2), resist 10 (and poly 8) serving as the mask. The implant is done across SiO2 6, and arsenic is the preferred N+ impurity. Now undercut poly 8 as illustrated at 12, the typical lateral depth being about 0.4 mm (Fig. 2). - Remove resist 10, anneal the wafer and introduce N impurity 16 of relatively low or moderate concentration at the surface of substrate 2, poly 8 serving as the mask. Ion implantation across SiO2 6 is used for this purpose, arsenic being the preferred impurity (Fig. 3). - Form about 6000 A SiO2 18, preferably through chemical vapor deposition (C...