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Differential Cascode Current Switch Full Adder Look-Ahead Circuitry

IP.com Disclosure Number: IPCOM000044508D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 93K

Publishing Venue

IBM

Related People

Leininger, JC: AUTHOR

Abstract

This article describes a circuit arrangement which provides carry and propagate look-ahead circuitry so that sums may be obtained with minimum delay. Differential Cascode Current Switch (DCCS) and Cascode Voltage Switch (CVS) circuitry is often generated by software programs. The function that is desired is described in a high-level language and then decomposition programs are run to generate the individual circuits (trees). While these decomposition programs tend to give satisfactory results for random logic with few variables, large functions, such as full adders with many input variables, are not handled efficiently. The programs give results that have many more DCCS circuits than necessary and more stages of delay than desirable. Figs.

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Differential Cascode Current Switch Full Adder Look-Ahead Circuitry

This article describes a circuit arrangement which provides carry and propagate look-ahead circuitry so that sums may be obtained with minimum delay. Differential Cascode Current Switch (DCCS) and Cascode Voltage Switch (CVS) circuitry is often generated by software programs. The function that is desired is described in a high-level language and then decomposition programs are run to generate the individual circuits (trees). While these decomposition programs tend to give satisfactory results for random logic with few variables, large functions, such as full adders with many input variables, are not handled efficiently. The programs give results that have many more DCCS circuits than necessary and more stages of delay than desirable. Figs. 1A and 1B show two- bit carry DCCS circuits without and with an adder carry-in signal, respectively. Fig. 2 shows a 2-bit propagate DCCS circuit. These circuits are used as the first stage of any size full adder. Fig. 3 shows a DCCS circuit that allows 5 circuits of the type in Figs. 1 and 2 to be connected to obtain a group carry. Fig. 4 shows a DCCS circuit that provides a group propagate for 5-input propagate signals. Fig. 5 shows how the above circuits may be connected together to generate group carries and propagates for several different size full adders up to 50 bits wide with a maximum of 3 stages of delay. Once these carries and propagates are develope...