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True-Complement Generator for Dynamic Arrays

IP.com Disclosure Number: IPCOM000044509D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Bernstein, K: AUTHOR

Abstract

The advent of microprocessors, which digest 32-bit data words, requires logic macros to accomplish their function in minimum area and power. This article describes a circuit which provides true and complement signal to dynamic branch-on-bit (BOB) logic arrays and allows proper restore during all non-active phases. The dynamic branch-on-bit array (Fig. 1) performs tree decoding by outputting on node "BOB" one bit selected from the 32 input bits 01CO through 32CO. This is done with five levels of one-of-two selects where each level requires the true and complement forms of the input address associated with that level. Address 5 is the least significant level, reducing the array from 32 selectable nodes to 16 selectable nodes via the one-of-two select performed by address-5-true and address-5-complement.

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True-Complement Generator for Dynamic Arrays

The advent of microprocessors, which digest 32-bit data words, requires logic macros to accomplish their function in minimum area and power. This article describes a circuit which provides true and complement signal to dynamic branch-on-bit (BOB) logic arrays and allows proper restore during all non-active phases. The dynamic branch-on-bit array (Fig. 1) performs tree decoding by outputting on node "BOB" one bit selected from the 32 input bits 01CO through 32CO. This is done with five levels of one-of-two selects where each level requires the true and complement forms of the input address associated with that level. Address 5 is the least significant level, reducing the array from 32 selectable nodes to 16 selectable nodes via the one-of-two select performed by address-5-true and address-5-complement. The inputs are grouped in pairs, with one of the pair's gates selected by the true version and the other selected by the complement version of address 5. Address 4 is the next least significant level, reducing the array from 16 selectable nodes (level 5 output) to 8 selectable nodes in the same fashion as level 5. There are half as many device pairs in this level as in the last and this hierarchy continues to level one, the most significant level. Level one performs one one-of-two select to choose which half of the array's output is the true selected bit. The output of this level is forwarded to a clocked output driver which traps the state of the output bit at the end of the active cycle, thus allowing restoration of the array while data is still held valid. The array is dynamic in that a path to ground is either provided or denied to dynamic node "BOB" through five levels of addressing. Note that this ground connection is provided at nodes 01CO through 32CO by 32 circuits (Fig. 2). If ...