Browse Prior Art Database

Circuit for Mapping Small Blocks of Large Memory Address Spaces

IP.com Disclosure Number: IPCOM000044514D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 66K

Publishing Venue

IBM

Related People

Lloyd, RP: AUTHOR [+2]

Abstract

This article describes a test circuit that allows the recording of testcase coverage of a small memory address block (64K) that is part of a large memory address space, typically 32 bits (4096K). Mapping of instruction execution is a technique used in the testing of computer system software and microcode. Mapping is a process by which memory addresses executed are flagged and displayed in an X-Y plane which contains all the possible memory addresses. Systems with small address spaces (16- to 20-bit address lines) can be mapped straight forward with a hardware mapper which has a memory capacity of 64K by 1 bit to 1024K by 1 bit. Newer computer systems, though, have address line capacity of 32 bits which means a mapper is required with a 4,298,080K by 1 bit capacity.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 2

Circuit for Mapping Small Blocks of Large Memory Address Spaces

This article describes a test circuit that allows the recording of testcase coverage of a small memory address block (64K) that is part of a large memory address space, typically 32 bits (4096K). Mapping of instruction execution is a technique used in the testing of computer system software and microcode. Mapping is a process by which memory addresses executed are flagged and displayed in an X-Y plane which contains all the possible memory addresses. Systems with small address spaces (16- to 20-bit address lines) can be mapped straight forward with a hardware mapper which has a memory capacity of 64K by 1 bit to 1024K by 1 bit. Newer computer systems, though, have address line capacity of 32 bits which means a mapper is required with a 4,298,080K by 1 bit capacity. This is physically impossible to achieve in a mapper using existing technology. The circuit shown in Fig. 1 can be used to map small address segments (64K by 1 bit to 1024K by 1 bit) of a large (32-bit) address space. This circuit is based on off-line control by a microprocessor or small computer through a control bus 1 and a 16-bit data bus 2. The segment to be mapped is loaded from the controlling system into the high-order select register 3. The output of this register is fed to the high-order comparator 4. During on-line operation the mapping circuit is connected to the address bus and address valid line of the system under test (SUT) via probes (not shown). The low-order address bits 5 are connected to the map memory address multiplexer 6 which drives the map memory 7. A collector dot or tri-state configuration is not...