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Diode Doubling

IP.com Disclosure Number: IPCOM000044515D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Reynolds, CB: AUTHOR

Abstract

Diode doubling for high drive applications increases the effectiveness of pulldown devices, improving both performance and density. In conventional NMOS circuits, the maximum drive capability is gated by the area required for the output-stage pulldown devices (particularly for wide NOR, NAND and AOI/OAI configurations). The addition of an enhancement-mode device (EMD) or zero threshold device (ZVT) 11, as shown, allows the initial stage pulldowns (devices 2-5) to assist in the discharge of output capacitance - reducing the effective width-to-length ratio required of devices 7-10. This technique is employed in enhanced clock driver designs, where it was shown, via circuit simulation, to improve falling delays by approximately 20%.

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Diode Doubling

Diode doubling for high drive applications increases the effectiveness of pulldown devices, improving both performance and density. In conventional NMOS circuits, the maximum drive capability is gated by the area required for the output-stage pulldown devices (particularly for wide NOR, NAND and AOI/OAI configurations). The addition of an enhancement-mode device (EMD) or zero threshold device (ZVT) 11, as shown, allows the initial stage pulldowns (devices 2-5) to assist in the discharge of output capacitance - reducing the effective width-to-length ratio required of devices 7-10. This technique is employed in enhanced clock driver designs, where it was shown, via circuit simulation, to improve falling delays by approximately 20%. The benefits of this concept are illustrated in the table below - comparing the performance of conventional vs. diode doubled, direct-drive ORed clock drivers. Both circuits occupy similar layout areas (1 standard cell) and dissipate similar DC power.

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Note: Conventional OR circuit has 2 inputs, whereas diode doubled (direct drive) has 3 inputs. The OR circuit indicated in the table, as well as other (NAND, AND and NOR) clock driver books employing diode doubling (DD) may be readily included into a Si gate standard cell library. The use of DD enables these books to be layed out in one standard cell (roughly 4500 mm2). This could not be achieved without DD, as the output pulldown devices then prove to be too...