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Josephson Two-Squid "Negative" Logic Latch

IP.com Disclosure Number: IPCOM000044520D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Heidel, DF: AUTHOR

Abstract

A two-SQUID negative logic Josephson latch circuit eliminates the need for dual-rail control signals, increases operating tolerances, and makes the latch compatible with other Josephson logic circuits. Fig. 1 shows a latch circuit that uses as write gates two SQUIDS 1 and 2 in the storage loop, and uses a form of "negative" logic to remove the requirement for dual-rail control signals. The Truth Table is shown in Fig. 2. It is necessary to clarify what is meant by "negative" logic in this context. Josephson logic circuits operate on positive logic. A high current level represents a logical "1"; a low current level represents a logical "0." This new latch uses negative logic, meaning that a stored current represents a logical "0" and no stored current represents a logical "1." As can be seen in Fig.

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Josephson Two-Squid "Negative" Logic Latch

A two-SQUID negative logic Josephson latch circuit eliminates the need for dual-rail control signals, increases operating tolerances, and makes the latch compatible with other Josephson logic circuits. Fig. 1 shows a latch circuit that uses as write gates two SQUIDS 1 and 2 in the storage loop, and uses a form of "negative" logic to remove the requirement for dual-rail control signals. The Truth Table is shown in Fig. 2. It is necessary to clarify what is meant by "negative" logic in this context. Josephson logic circuits operate on positive logic. A high current level represents a logical "1"; a low current level represents a logical "0." This new latch uses negative logic, meaning that a stored current represents a logical "0" and no stored current represents a logical "1." As can be seen in Fig. 2, it is possible to combine the "negative" logic latch with the standard "positive" logic circuits and use only SET control signal(s) to control the latch. The method of combining the circuits consists of using the DATA (D) signal to erase stored currents rather than write a stored current and to exchange the dual-rail outputs of a slave circuit 3 (i.e., TTC, CTT). The operation of the latch is: An AND operation is performed on the S and D signals by AND gate 4 and then used to erase any circulating currents in the storage loop by switching gate 5. If S*D=1, no current can be stored in the latch and thus the output in the nex...