Browse Prior Art Database

High-Frequency LSSD Clock Generator

IP.com Disclosure Number: IPCOM000044541D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Awsienko, O: AUTHOR [+2]

Abstract

A technique is described whereby a high-frequency clock generator is designed for compatibility with level sensitive scan design (LSSD) technology. The design provides the following significant features: 1. Clock generation on a single chip greater than 20 MHz 2. Full LSSD compatibility 3. High testability (99.85 percent) 4. Testability is achieved with automatic test pattern generators 5. Clock symmetry is independent of oscillator symmetry 6. Minimum variation in clock pulse width 7. No special modules or circuits are required. The functional operation of the clock generator, as shown in the block diagram of Fig. 1, is to achieve precise control over the pulse width of the clock.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 69% of the total text.

Page 1 of 2

High-Frequency LSSD Clock Generator

A technique is described whereby a high-frequency clock generator is designed for compatibility with level sensitive scan design (LSSD) technology. The design provides the following significant features: 1. Clock generation on a single chip greater than 20 MHz 2. Full LSSD compatibility 3. High testability (99.85 percent) 4. Testability is achieved with automatic test pattern generators 5. Clock symmetry is independent of oscillator symmetry 6. Minimum variation in clock pulse width 7. No special modules or circuits are required. The functional operation of the clock generator, as shown in the block diagram of Fig. 1, is to achieve precise control over the pulse width of the clock. By using clock decoder 10 to control the output of divide-by-two circuits 11 and 12, the clock pulse width is independent of the oscillator symmetry. Since the leading and trailing edge of the clock is produced from the leading edge of the oscillator, this results in a minimum variation in clock pulse width. The outputs C1 to C4 of clock repower circuit 13 can be seen in the timing chart of Fig. 2. The divide-by-two circuits 11 and 12 utilize latches L1 and L2*, as shown in Fig. 3, to provide the testability and feedback controls required in LSSD circuitry. The output-to-input feedback of the latches is eliminated by providing gate signal T4 at the latch data ports. During system operation, T4 is tied to the enable state and, during testing, T4 is ti...