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Design of Early Error Detection for Memory

IP.com Disclosure Number: IPCOM000044550D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Sitler, WR: AUTHOR [+2]

Abstract

This is a design to prevent data loss in memory by detecting defective memory/array locations during data write operations. It can be built into either an array chip for memory chip design or put into a system hardware for computer systems which use regular memory chips. In most array chips, the read operation can be performed during or after a write operation (Fig. 1). There is a timing delay between the beginning of valid input data and the beginning of the same valid output data. This delay varies with different array chips. The design takes both the input data and the output data of an array chip and conducts a logical exclusive OR (XOR) after the timing delay. If the result of the XOR is a logical 0, the write operation is successful and no errors are detected.

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Design of Early Error Detection for Memory

This is a design to prevent data loss in memory by detecting defective memory/array locations during data write operations. It can be built into either an array chip for memory chip design or put into a system hardware for computer systems which use regular memory chips. In most array chips, the read operation can be performed during or after a write operation (Fig. 1). There is a timing delay between the beginning of valid input data and the beginning of the same valid output data. This delay varies with different array chips. The design takes both the input data and the output data of an array chip and conducts a logical exclusive OR (XOR) after the timing delay. If the result of the XOR is a logical 0, the write operation is successful and no errors are detected. However, if the result of the XOR is a logical 1, a mismatch is found and it may indicate a defective array location (Fig. 2). During the write operation, besides activating the write control line, the read control line should also be activated. If the read and write controls are on the same signal line in some array chips, the signal should be shifted to read control right after the write control is finished. The output signal lines from the XOR are connected to a logical OR gate and eventually connected to a machine check circuitry which will stop normal program execution and start a retry program that will reissue the failed operation and a write operation...