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High Yield Anneal for Gallium Arsenide Wafers

IP.com Disclosure Number: IPCOM000044556D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Robbins, GJ: AUTHOR

Abstract

This is a method of increasing yields of gallium arsenide (GaAs) wafers by tailoring the process to the particular properties of individual wafers as opposed to blanket process specifications. The proposed method is to individually characterize wafers and define implants specific to each wafer and to specific areas upon a wafer. The GaAs MESFET (metal Schottky FET) device has practical, high performance applications in future digital integrated circuits, but suffers from switching threshold voltage (VTH) process variations which limit yield and cause performance tradeoffs. This is due to variations in wafer background impurities, sensitivity of VTH as square of chemical depth, proportional to channel doping and Schottky diode forward voltage variations.

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High Yield Anneal for Gallium Arsenide Wafers

This is a method of increasing yields of gallium arsenide (GaAs) wafers by tailoring the process to the particular properties of individual wafers as opposed to blanket process specifications. The proposed method is to individually characterize wafers and define implants specific to each wafer and to specific areas upon a wafer. The GaAs MESFET (metal Schottky FET) device has practical, high performance applications in future digital integrated circuits, but suffers from switching threshold voltage (VTH) process variations which limit yield and cause performance tradeoffs. This is due to variations in wafer background impurities, sensitivity of VTH as square of chemical depth, proportional to channel doping and Schottky diode forward voltage variations. Compensating anneal doses by sacrificing neighbor-sliced wafers for pre- process dope-anneal and subsequent recalibration of equipment is the most sophisticated approach practiced to date. However, entire wafers are destroyed and the accuracy is not as good as if each wafer were individually compensated. This proposal is to devote a small section of each wafer for flash spot anneal after doping to minimal dopant level. This anneal could possibly be performed without removing the wafer from implanter using, e.g., laser flash-anneal or special separate equipment. Subsequent non-contactless or contacted resistivity measurement followed by subsequent additional implant/fla...