Browse Prior Art Database

Logic Level Detection Using Strobing Detector

IP.com Disclosure Number: IPCOM000044569D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Young, DC: AUTHOR [+2]

Abstract

Testers that can only strobe a response signal at a given time cannot monitor responses over a specified "time window" within a tester cycle. Unless the time between strobe samples is small, there is a possibility that the tester will not detect a glitch. The following program board circuit, when inserted between the tester and the device under test (DUT) pins, provides the capability to monitor a logic signal within a window as defined by DELAY and WIDTH. The program board circuit contains the following circuit blocks: 1. An exclusive OR 11 for latching the D-latch 12 or 13 when the tester driver signal (DR) 14 and the DUT output (PO) 15 have different logic levels. 2. A D-latch 12 for detecting any level changes during the monitor window, where a stable logic level is expected.

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Logic Level Detection Using Strobing Detector

Testers that can only strobe a response signal at a given time cannot monitor responses over a specified "time window" within a tester cycle. Unless the time between strobe samples is small, there is a possibility that the tester will not detect a glitch. The following program board circuit, when inserted between the tester and the device under test (DUT) pins, provides the capability to monitor a logic signal within a window as defined by DELAY and WIDTH. The program board circuit contains the following circuit blocks: 1. An exclusive OR 11 for latching the D-latch 12 or 13 when the tester driver signal (DR) 14 and the DUT output (PO) 15 have different logic levels. 2. A D-latch 12 for detecting any level changes during the monitor window, where a stable logic level is expected. The Q output 16 goes to a logic 1 whenever the DUT PO 15 changes its logic level in that timing window. The CLR 17 is low active and is used for resetting the D- latch 12 when the tester DR 14 is a logic O. This latch 12 is used for monitoring positive logic levels. 3. A D-latch 13 for detecting any level changes during the monitor window. The Q output 18 goes to a logic 1 whenever the DUT PO 15 changes its logic level in that timing window. The CLR 19 is high active and is used for resetting the D-latch 13 when the tester DR 14 is a logic 1. This latch 13 is used for monitoring negative logic levels. 4. A multiplexer 20 for detecting when th...