Browse Prior Art Database

Complement Address Generation

IP.com Disclosure Number: IPCOM000044575D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Beha, H: AUTHOR

Abstract

Controlling a complement address as a function of the true address permits the use of a simple single-gate-per-bit complement generator in a Josephson read-only memory (ROM). Memory system requirements may require the true and complement of the stored words. The basic complement address generation scheme is shown in Fig. 1, where the true address coming from the word-organized ROM array (from sense bus) controls the complement address gates (CAGs). The complement address gates are DC-powered and connected in series. Isolation resistors Ri are introduced to minimize disturbs caused by the simultaneous switching of CAGs receiving a binary "0".

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 84% of the total text.

Page 1 of 2

Complement Address Generation

Controlling a complement address as a function of the true address permits the use of a simple single-gate-per-bit complement generator in a Josephson read- only memory (ROM). Memory system requirements may require the true and complement of the stored words. The basic complement address generation scheme is shown in Fig. 1, where the true address coming from the word- organized ROM array (from sense bus) controls the complement address gates (CAGs). The complement address gates are DC-powered and connected in series. Isolation resistors Ri are introduced to minimize disturbs caused by the simultaneous switching of CAGs receiving a binary "0". The complement address gate is an asymmetric two-junction interferometer where the current IDCC is inserted directly at the smaller Josephson junction, resulting in threshold characteristics, as shown in Fig. 3. As shown, CAG is controlled by two input signals with different polarities. After the application of the address signals, the current ID is switched on to activate the complement address gates which are switching to the voltage state if the binary information "0", Is= 0 has been applied, and transferring current ICL into the output loop, corresponding to the binary "1". The trigger signal ID can be a level signal as well as a pulse signal. Hence, the load of the CAG can be realized either as a loop inductance, which requires a reset gate in the loop, or as a L/R-load, which allows a sel...