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Improved Branch History Table Operations

IP.com Disclosure Number: IPCOM000044578D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Emma, PG: AUTHOR [+4]

Abstract

This article describes a method of altering the sequence of update and interrogate operations, to reduce Branch Wrong Guess Penalty in a branch history table (BHT). For a processor with a BHT which is used to anticipate branch action (taken/not taken) and branch target, the policy of update and interrogate following a branch wrong guess (BWG) can affect both the duration of the penalty and the frequency of the BWG. Assuming that update and interrogate cannot be done in parallel, the optimum policy is to defer the update until the first occurrence of two successive misses within the BHT. The rationale for this is as follows: Two successive misses by the BHT cause SEQUENTIAL I - FETCHING which is not susceptible to breakage (instruction crossing, DW/QW boundaries). Delaying interrogate adds a cycle to branch penalty.

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Improved Branch History Table Operations

This article describes a method of altering the sequence of update and interrogate operations, to reduce Branch Wrong Guess Penalty in a branch history table (BHT). For a processor with a BHT which is used to anticipate branch action (taken/not taken) and branch target, the policy of update and interrogate following a branch wrong guess (BWG) can affect both the duration of the penalty and the frequency of the BWG. Assuming that update and interrogate cannot be done in parallel, the optimum policy is to defer the update until the first occurrence of two successive misses within the BHT. The rationale for this is as follows: Two successive misses by the BHT cause SEQUENTIAL I - FETCHING which is not susceptible to breakage (instruction crossing, DW/QW boundaries). Delaying interrogate adds a cycle to branch penalty. Not interrogating with new target can increase frequency of BWG. The probability of such a BWG increases with the access width to the cache. A buffer maintains the deferred update and is cleared by the next BWG. It can be accessed in parallel with BHT, if required.

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