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Browse Prior Art Database

Staggering of the Precharge Clocks in Domino Circuits

IP.com Disclosure Number: IPCOM000044581D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 85K

Publishing Venue

IBM

Related People

Boudon, G: AUTHOR

Abstract

The circuit shown in the drawings allows the noise which is due to the current switching in circuits of the Domino type to be minimized. As shown in Fig. 1, the circuits of the Domino type require a clock PC for precharging the logic circuits. When this clock is at a low level, all nodes 1 of the logic circuits, located between two register blocks L1 and L2, are at a high level while the buffer outputs X and Y are at a low level. When clock PC switches to the high level, the logical circuits start to operate and the data are propagated such that high levels are generated at the energized buffer outputs. Once the propagation of the data is terminated, the result is loaded into the first stage L1 of the register by clock C1 and in slave stage L2 by clock B.

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Staggering of the Precharge Clocks in Domino Circuits

The circuit shown in the drawings allows the noise which is due to the current switching in circuits of the Domino type to be minimized. As shown in Fig. 1, the circuits of the Domino type require a clock PC for precharging the logic circuits. When this clock is at a low level, all nodes 1 of the logic circuits, located between two register blocks L1 and L2, are at a high level while the buffer outputs X and Y are at a low level. When clock PC switches to the high level, the logical circuits start to operate and the data are propagated such that high levels are generated at the energized buffer outputs. Once the propagation of the data is terminated, the result is loaded into the first stage L1 of the register by clock C1 and in slave stage L2 by clock B. In this circuit the simultaneous switching of the supply current produces an important noise, particularly when the number of the switched circuits is high. This current is of high value during the precharge period when all the circuits which have been switched during the logic operation are reset simultaneously to the initial "0" state. To prevent this from happening a circuit (Fig. 2) is provided for generating a plurality of precharge clocks PC1, PC2 and PC3, such as shown in the timing diagram in Fig. 3. These clocks are generated from clocks C1 and B which control the registers, by means of NOR and INVERTER circuits and a latch of the reset/set type. To...