Browse Prior Art Database

Silicon-On-Insulator for Soft Error Rate Reduction

IP.com Disclosure Number: IPCOM000044601D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

El-Kareh, B: AUTHOR [+2]

Abstract

This article describes a means to shield circuit nodes from carriers generated by energetic particles. With reference to Fig. 1, the cell nodes in a "four-square" dynamic RAM configuration [*] can be upset if carriers generated in the silicon bulk by energetic particles, such as alpha particles or cosmic rays, are collected by the nodes. The shielding of the nodes consists of placing a blocking insulator between the nodes and the silicon bulk. This is illustrated in Fig. 2. The "seed pedestals or regions," as described below, connect the substrate to the silicon-on-insulator p regions. Those "seed pedestals" are placed under the n+ "fill-and-spill" pockets, allowing the n+ pockets which are insensitive to carrier collection to serve as sinks for the generated carriers that infiltrate through the seed region.

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Silicon-On-Insulator for Soft Error Rate Reduction

This article describes a means to shield circuit nodes from carriers generated by energetic particles. With reference to Fig. 1, the cell nodes in a "four-square" dynamic RAM configuration [*] can be upset if carriers generated in the silicon bulk by energetic particles, such as alpha particles or cosmic rays, are collected by the nodes. The shielding of the nodes consists of placing a blocking insulator between the nodes and the silicon bulk. This is illustrated in Fig. 2. The "seed pedestals or regions," as described below, connect the substrate to the silicon- on-insulator p regions. Those "seed pedestals" are placed under the n+ "fill-and- spill" pockets, allowing the n+ pockets which are insensitive to carrier collection to serve as sinks for the generated carriers that infiltrate through the seed region. Note that the upper recessed oxide regions (TOP ROX) could be extended to merge with the lower recessed oxide (ROX-1) regions for further isolation. The main processing steps are described as follows: 1. Deposit an oxide/nitride layer over a starting P type wafer 11, as shown in Fig. 3. 2. Define "seed pedestals" 12 in the oxide/nitride layer, and etch the oxide/nitride in the regions outside the pedestals. 3. Grow the recessed oxide (ROX 1) layers 13. The presence of nitride inhibits the oxide from growing in the seed regions (Fig. 4). 4. Remove the thin insulators in the seed regions, deposit p type polys...