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Low Temperature Interferometer Array Accessing

IP.com Disclosure Number: IPCOM000044604D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Feder, JD: AUTHOR [+2]

Abstract

Two-dimensional configuration of low temperature integrated circuit arrays maximizes the number of devices accessible by a limited number of access ports during testing. A test vehicle designed to gather a statistically significant quantity of data on device parameters is often limited in the number of accessible devices by the number of I/O ports. This article details a method which maximizes (with respect to the available I/O) the number of Josephson junction devices accessible to measurement. The Josephson interferometers 1 are arranged in a two-dimensional array on the chip (see the figure). Individual devices are singled out by the selective application of gate and control currents via lines connected to the rows A-D and columns A'-D' of the array.

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Low Temperature Interferometer Array Accessing

Two-dimensional configuration of low temperature integrated circuit arrays maximizes the number of devices accessible by a limited number of access ports during testing. A test vehicle designed to gather a statistically significant quantity of data on device parameters is often limited in the number of accessible devices by the number of I/O ports. This article details a method which maximizes (with respect to the available I/O) the number of Josephson junction devices accessible to measurement. The Josephson interferometers 1 are arranged in a two-dimensional array on the chip (see the figure). Individual devices are singled out by the selective application of gate and control currents via lines connected to the rows A-D and columns A'-D' of the array. The technique allows the measurement of threshold characteristics and I-V properties of a large number of devices. Previous array concepts have kept the I/O lines supplying control currents independent of the gate current lines. Thus, an array with N columns by N rows required N I/O for gate currents plus N I/O for control currents (plus a small number of auxiliary leads); i.e., one obtained approximately N x N devices with 2N I/O. With the arrangement illustrated in the figure, each gate line also serves as a control line (these will be called Address Lines, or ALs). These ALs, along with a Global Control Line (GCL) which crosses every device in the array, render nearly every device in a square array accessible to measurement. There are no devices located on the diagonal of the array, since it would be impossible to have independently controlled gate and control currents there. Hence, this scheme allows the measurement of N(N-1) interferometers with only N+3 I/O pads. Each I/O pad is...