Browse Prior Art Database

Triple-Poly Shared Word Line Cell

IP.com Disclosure Number: IPCOM000044608D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 58K

Publishing Venue

IBM

Related People

Plass, DW: AUTHOR

Abstract

Cross-polysilicon technology and the shared word line concept are combined with a dual-gate I/O device for the cell to eliminate the double read operation and consequent long cycle time of the double-polysilicon version while retaining some of the key features. The dual-gate structure functions as two transistors in series to provide decoding at the cell level for dynamic random-access memories (RAMs). The implementation of this concept requires three levels of poly silicon: one for the cell plate, a second for the bit line and select line (secondary gate), and a third level for the word line (primary gate). The second level is also used as a field shield for isolation at the 'back door' of the cell while recessed oxide (ROX) is employed for isolation in the word dimension.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 72% of the total text.

Page 1 of 2

Triple-Poly Shared Word Line Cell

Cross-polysilicon technology and the shared word line concept are combined with a dual-gate I/O device for the cell to eliminate the double read operation and consequent long cycle time of the double-polysilicon version while retaining some of the key features. The dual-gate structure functions as two transistors in series to provide decoding at the cell level for dynamic random-access memories (RAMs). The implementation of this concept requires three levels of poly silicon: one for the cell plate, a second for the bit line and select line (secondary gate), and a third level for the word line (primary gate). The second level is also used as a field shield for isolation at the 'back door' of the cell while recessed oxide (ROX) is employed for isolation in the word dimension. This approach achieves an alignment-insensitive cell capacitor. The basic operation is as follows (polarities assume N type MOS): - Each Poly 2 Bit Line is surrounded by Poly 2 Select Lines running in parallel. On any cycle, one of the two select lines is brought high, turning on one half of the dual-gate structure and redistributing the cell charge between the Poly 1 capacitor and the Poly 2 gate. If the corresponding Poly 3 Word Line rises, the other half of the dual gate is on and electrons will flow out to the N-skin bit line for a stored zero. (N-skin is a self- aligned diffusion under a polysilicon gate.) - For cells which are along unaccessed Word Lines...