Browse Prior Art Database

Method for Optimizing Logic for Single-Ended Domino Logic Circuits

IP.com Disclosure Number: IPCOM000044609D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Brayton, RK: AUTHOR [+3]

Abstract

This publication describes a method of eliminating redundancy in the logic by removing some of the phases of the internal signals employing a technique of decomposing the logic using a single-ended decomposition technique using a method of assigning the output phases so as to minimize the number of inverts required. Inverts remaining are implemented in single-ended trees. This provides an "invert-free" implementation, which is then decomposed and compressed using the single-ended decomposition strategy. Differential trees can be used at this stage to implement complementary signals if the number of trees and transistors required does not increase over the single-ended implementation. A constraint of using CMOS circuits, as proposed by Krambeck, et al.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 3

Method for Optimizing Logic for Single-Ended Domino Logic Circuits

This publication describes a method of eliminating redundancy in the logic by removing some of the phases of the internal signals employing a technique of decomposing the logic using a single-ended decomposition technique using a method of assigning the output phases so as to minimize the number of inverts required. Inverts remaining are implemented in single-ended trees. This provides an "invert-free" implementation, which is then decomposed and compressed using the single-ended decomposition strategy. Differential trees can be used at this stage to implement complementary signals if the number of trees and transistors required does not increase over the single-ended implementation. A constraint of using CMOS circuits, as proposed by Krambeck, et al. [*] to form a domino chain is to ensure that all the inputs to the domino chain ar "domino gate" type of signals, i.e., signals which are at ground potential during precharge. If not, a precharge node may leak away its charge resulting in a wrong signal propagated along the domino chain. This is called the Non- Domino-Gate (NDG) problem. In the technique described herein, NDG signals which are created by an automatic logic decomposition algorithm are eliminated. A typical output of the automatic logic decomposition method is shown in Fig. 1. There are 15 domino trees, as expressed in equation 1 to equation 15. Each domino tree consists of some primary input (A to M) and some internally generated domino signals (N to T). The "+" and "-" signs associated with an internally generated signal reflect the use of "true" and "complement" signals, respectively, in this logic decomposition. The "*" means that both true and complement signals are used. The existence of complement signals implies the possibility of having an NDG problem. A fan-in, fan-out (FI/FO) map is shown in Fig. 2. This FI/FO map shows the logic stages of the delays among internally generated signals. A higher level in the FI/FO map reflects more delay. Level 0 signals are the primary inputs, which level 4 signals are the outputs of this domino chain. It is assumed that the primary inputs are obtained from registers or other devices from which both the true and complement signals are available. It is also assumed that the primary outputs are fed to registers or other devices, so that freedom exists to implement either the true or complement of an output. The register will provide the other phase. The primary outputs are partitioned in two categories; (a) those outputs which are also used as intermediate internal signals and (b) those outputs which only feed an output register. This latter set of outputs is denoted by the symbol O. Also, let n designate the number of outputs of this type. The other outputs will be treated just like any internal signal. The set of internal signals including the first type of output will be denoted by I. A signal, x, directly d...