Browse Prior Art Database

Serial-Access Page-Mode Memory

IP.com Disclosure Number: IPCOM000044622D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

This article describes a method of reducing the cost of large backing stores by eliminating the column decoder and associated support circuitry. The rows of sense amplifiers (SAs) function as a serial-access memory by the addition of very little circuitry. Since the backing store applications require the transfer of blocks of data "pages", the system can accept the reduced flexibility of the memory. The memory chip structure can still provide adequate data rates because the cycle time for the sequential data access is much shorter than standard cycle times. The serial-access page-mode memory disclosed here can be designed with an eight-device SA without a column decoder, as shown in the memory design. Far fewer decoders, i.e., block decoders 10, serving to select blocks of sense amplifiers, would be needed.

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Serial-Access Page-Mode Memory

This article describes a method of reducing the cost of large backing stores by eliminating the column decoder and associated support circuitry. The rows of sense amplifiers (SAs) function as a serial-access memory by the addition of very little circuitry. Since the backing store applications require the transfer of blocks of data "pages", the system can accept the reduced flexibility of the memory. The memory chip structure can still provide adequate data rates because the cycle time for the sequential data access is much shorter than standard cycle times. The serial-access page-mode memory disclosed here can be designed with an eight-device SA without a column decoder, as shown in the memory design. Far fewer decoders, i.e., block decoders 10, serving to select blocks of sense amplifiers, would be needed. Note that devices 3A, 3B, 6A and 6B are shared with adjacent SAs. All odd SAs (SA1) have precharge 1, all even SAs (SA2) have precharge 2. The SAs form a string of latches that can act as a shift register. All the data from the odd or even SAs can be shifted out and read at the end by the block decoder by pulsing precharge, transfer and sense latch lines, as described in more detail below. The sequence of operations is as follows: 1. Load isolator drops after the SA operation is complete and the word line has fallen to store back the data. 2. Precharge 2 rises and sense latch pulse 2 rises to VDD. 3. Precharge 2 falls and SA2 nod...