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Switchable Up-Level Clamp Circuit

IP.com Disclosure Number: IPCOM000044629D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Chan, YH: AUTHOR

Abstract

Background In high density, high performance arrays using CTS cells [*], the voltage mode word selection scheme is preferred over the conventional constant current source technique. The key advantages of voltage mode operation are faster performance and better stability. The proper operation of a voltage mode word selection design requires a bit-up-level clamp reference which has to track with the selected word line cells. The bit-level clamp reference serves two functions: (1) set an operating point for the selected cell during read (i.e., to guarantee IL and IG currents into a READ cell under all environments) and (2) control and perform the write function. Disclosed here is a switchable bit-up-level clamp circuit designed for CTS arrays operating in voltage mode.

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Switchable Up-Level Clamp Circuit

Background In high density, high performance arrays using CTS cells [*], the voltage mode word selection scheme is preferred over the conventional constant current source technique. The key advantages of voltage mode operation are faster performance and better stability. The proper operation of a voltage mode word selection design requires a bit-up-level clamp reference which has to track with the selected word line cells. The bit-level clamp reference serves two functions: (1) set an operating point for the selected cell during read (i.e., to guarantee IL and IG currents into a READ cell under all environments) and (2) control and perform the write function. Disclosed here is a switchable bit-up-level clamp circuit designed for CTS arrays operating in voltage mode. The reference level generated by this circuit has the following two features: (1) It tracks with the selected word line cells in temperature, power supply (VEE) and device variations (VBE). (2) It can be switched to generate both a READ and a WRITE reference. Circuit Description Fig. 1 illustrates a voltage mode word selection scheme for CTS arrays. The operating point of a READ cell is determined by the following equations: VCLM = VEE + VBE(TD) - VF(SD) + VBE(TR) + VF(SL) + V(RBL) + VBE(T1) - VBE(TC) VCLM = VEE + 2VBE + V(RBL) (1) IG = V(RBL)/RBL ; IL = V(RBR)/RBR Fig. 2 shows the schematic of this bit-up-level clamp circuit. The circuit has a control input (R/W) which selects between a READ (R) or a WRITE (W) reference level. (I) READ R/W input is high (T1 ON and T2 OFF). Device T3 is turned ON to set a READ reference level. Vref (READ) = VEE + VBE(T5) + VBE(T4) +VBE(T3) - VF(S3)...