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Browse Prior Art Database

Microcode Patch Method for a Multiplicity of Processors

IP.com Disclosure Number: IPCOM000044630D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 75K

Publishing Venue

IBM

Related People

Roop, DA: AUTHOR

Abstract

A method which allows multiple processors to share a patch source has these basic elements: 1) synchronous, but phase-shifted, operation of the processors, 2) multiplexing of the processor address busses into the patch source and demultiplexing the patch source data to the processors, and 3) an additional address vector presented to the custom Decode PROM (Programmable Read-Only Memory) which identifies the processor accessing the patch source. Fig. 1 depicts a general multiple processor system in which the patch source 2 is shared among the processors. The ID encoder 3 is responsible for creating a unique address for each processor 5 in the system. This unique address is used along with the high-order portion of the processor's memory address bus to access the portion of the Decode PROM 4 allocated to that processor.

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Microcode Patch Method for a Multiplicity of Processors

A method which allows multiple processors to share a patch source has these basic elements: 1) synchronous, but phase-shifted, operation of the processors,
2) multiplexing of the processor address busses into the patch source and demultiplexing the patch source data to the processors, and 3) an additional address vector presented to the custom Decode PROM (Programmable Read- Only Memory) which identifies the processor accessing the patch source. Fig. 1 depicts a general multiple processor system in which the patch source 2 is shared among the processors. The ID encoder 3 is responsible for creating a unique address for each processor 5 in the system. This unique address is used along with the high-order portion of the processor's memory address bus to access the portion of the Decode PROM 4 allocated to that processor. The operating cycles of the processors must be phase-shifted with respect to one another to allow each processor a time slot in which to access the patch source (Fig. 2). These time slots for the individual processors overlay the time of the processor's normal ROS access. One bit in each code word of the Decode PROM is used to enable the Patch Source and disable the ROS or enable the ROS and disable the Patch Source. The advantages of using the proposed patch method for multiple processors can be seen when it is compared to the commonly used method of substituting a EPROM module for a ROS modu...