Browse Prior Art Database

Display Processor Memory Addressing

IP.com Disclosure Number: IPCOM000044635D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bantz, DF: AUTHOR [+3]

Abstract

This invention allows display processors to access image memory efficiently. Display processors may use two pairs of (X,Y) registers to address the image memory which is arranged as a two-dimensional array of pixels (picture elements). The display processor can choose one of the (X,Y) registers to perform a memory operation (either read or write the image memory). As a side effect the selected pair of registers can be independently incremented or decremented to be appropriately set up for the next memory cycle. This organization allows the efficient operation of algorithms which update the image memory such that successive memory cycles are in the two-dimensional local neighborhood of previous memory cycles.

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Display Processor Memory Addressing

This invention allows display processors to access image memory efficiently. Display processors may use two pairs of (X,Y) registers to address the image memory which is arranged as a two-dimensional array of pixels (picture elements). The display processor can choose one of the (X,Y) registers to perform a memory operation (either read or write the image memory). As a side effect the selected pair of registers can be independently incremented or decremented to be appropriately set up for the next memory cycle. This organization allows the efficient operation of algorithms which update the image memory such that successive memory cycles are in the two-dimensional local neighborhood of previous memory cycles. Conventional processors allow an easy access to memory which is in the local neighborhood by providing address incrementing or decrementing as a side-effect of memory operations. But these processors treat the memory space as a single-dimensional linear address space, and provide easy access to the single-dimensional linear neighborhood. A high-quality, high-performance display, with an image memory containing 640 x 820 pixels, represents each pixel by eight bits. The display processor is an eight- bit processor, and is designed to process one pixel at a time. The X and Y registers are each ten bits (to address the image memory), and can be independently incremented or decremented by one after each memory cycle. The two pai...