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Very Thin Dielectric Storage Cap in N-Skin Compatible Process

IP.com Disclosure Number: IPCOM000044639D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Scheuerlein, RE: AUTHOR

Abstract

Dynamic random-access memories (RAMs) in the range of 1 megabit to 4 megabits and beyond quite commonly have a diffused storage node and an implant of the opposite conductivity type, known as a HiC structure, added to the RAM cell to provide extra junction capacitance under the dielectric capacitance and also to provide a particle soft error rate reductions. One method of forming the diffused storage node is to implant dopant atoms into the storage dielectric and cause them to out-diffuse later in the process. This method is called an N-skin, which usually uses arsenic for the dopant atoms. This article describes a novel storage capacitor structure which uses the mask associated with the HiC implant for a dual purpose and allows the N-skin storage dielectric to shrink.

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Very Thin Dielectric Storage Cap in N-Skin Compatible Process

Dynamic random-access memories (RAMs) in the range of 1 megabit to 4 megabits and beyond quite commonly have a diffused storage node and an implant of the opposite conductivity type, known as a HiC structure, added to the RAM cell to provide extra junction capacitance under the dielectric capacitance and also to provide a particle soft error rate reductions. One method of forming the diffused storage node is to implant dopant atoms into the storage dielectric and cause them to out-diffuse later in the process. This method is called an N- skin, which usually uses arsenic for the dopant atoms. This article describes a novel storage capacitor structure which uses the mask associated with the HiC implant for a dual purpose and allows the N-skin storage dielectric to shrink. The conflicting requirements of increased doping levels in the N-skin and thinner dielectrics in which to implant the dopant atoms are difficult to meet, even at 150 ~ storage thickness. Higher doping levels are required by thinner storage dielectric to keep silicon depletion widths under the gate from growing. The HiC mask edge limits the boron implant to the storage region so that it does not increase the bit line capacitance or affect the I/O device threshold voltage in typical known designs. Here, the HiC mask also provides an opening over the storage region 16. Through the opening in the HiC mask, boron 10 is implanted and the stor...