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Concise Error Checking Circuit

IP.com Disclosure Number: IPCOM000044641D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Burbank, HC: AUTHOR [+4]

Abstract

A time and space efficient way is provided to compare logic signal validity. This concise error checking circuit performs chip signature checking or dual rail logic error checking. The logic inputs data in sets or pairs, i.e., A0, B0; A1, B1; A2 B2; etc. Any pair of inputs A1, B1 is propagated to the outputs P, P . If no A0, B0 pair exists, then any A1, B1 input pair is propagated to the outputs. If no A1, B1 or A0, B0 input pair exists then the logic computes the 2xi-way XOR of all inputs Ai, Bi. Thus, depending on the input variable values, this circuit performs one of three different multi-stage logic functions in only one stage of delay in a small area. The implementation shown is in a clocked differential cascode voltage switch family circuit.

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Concise Error Checking Circuit

A time and space efficient way is provided to compare logic signal validity. This concise error checking circuit performs chip signature checking or dual rail logic error checking. The logic inputs data in sets or pairs, i.e., A0, B0; A1, B1; A2 B2; etc. Any pair of inputs A1, B1 is propagated to the outputs P, P . If no A0, B0 pair exists, then any A1, B1 input pair is propagated to the outputs. If no A1, B1 or A0, B0 input pair exists then the logic computes the 2xi-way XOR of all inputs Ai, Bi. Thus, depending on the input variable values, this circuit performs one of three different multi-stage logic functions in only one stage of delay in a small area. The implementation shown is in a clocked differential cascode voltage switch family circuit.

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