Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Performance Transistor Structure

IP.com Disclosure Number: IPCOM000044666D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Jambotkar, CG: AUTHOR

Abstract

This article concerns a method for realizing very high performance transistors embodying a precisely aligned polysilicon emitter and extrinsic base. Through proper implementation of the scheme to be disclosed, high performance transistors with polysilicon emitters, shallow emitter junction depth, narrow basewidth, and precisely located heavy extrinsic base region doping can be formed. The essential portion of an NPN transistor resulting from the disclosed scheme appears in Fig. 7, with identifiers for reference. 1. In line with a current technology, N+ subcollector 4, N epi 8, P region 12 extending over both extrinsic and intrinsic base regions, base reox (recessed oxide) SiO2 14, and Si3N4 16 covering SiO2 14 are formed.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 52% of the total text.

Page 1 of 3

High Performance Transistor Structure

This article concerns a method for realizing very high performance transistors embodying a precisely aligned polysilicon emitter and extrinsic base. Through proper implementation of the scheme to be disclosed, high performance transistors with polysilicon emitters, shallow emitter junction depth, narrow basewidth, and precisely located heavy extrinsic base region doping can be formed. The essential portion of an NPN transistor resulting from the disclosed scheme appears in Fig. 7, with identifiers for reference.
1. In line with a current technology, N+ subcollector 4, N epi 8, P region 12 extending over both extrinsic and intrinsic base regions, base reox (recessed oxide) SiO2 14, and Si3N4 16 covering SiO2 14 are formed. Conventional device isolation schemes may be used as illustrated by the ROI SiO2 10 and P sub-isolation 6 beneath it. An N reach-through region (not shown) may also be formed. P12 is preferably formed by ion implant. Above Si3N4 16, deposit 0.5 - 1.0 mm SiO2 18 and through lithography, obtain tapered openings in SiO2 18, as illustrated in Fig. 1. The height and taper angle of SiO2 are suitably designed. 2. Using the SiO2 18 as a mask, etch exposed Si3N4 16 and the thin SiO2 14 beneath it. Then deposit a N .1 mm layer of polysilicon 20, which is doped N+ either in situ or preferably by subsequent ion implant, preferably using arsenic. The N+ dopant is then suitably driven into the monocrystal silicon to form the shallow N+ emitter regions 22 shown in Fig. 2. 3. A coat of a suitable viscous material 24, such as polyimide or photoresist, is formed above the structure of Fig. 2. Since the tapered windows in SiO2 18 are the small emitter openings, the material 24 provides a planar surface, as illustrated in Fig. 3. 4. The material 24 is preferably hardened at this stage through chemical or optical mea...