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RAM Internal Parallel Testing Technique

IP.com Disclosure Number: IPCOM000044671D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Cady, RC: AUTHOR [+3]

Abstract

A RAM (random-access memory) internal parallel testing technique adds circuits to a RAM chip to accomplish test time reduction by testing several addresses in parallel. Significant test time savings are achieved if chips and modules are organized to write and read in several parallel data input/output (DI/DO) channels, reducing the number of addresses that must be tested. To a first approximation, test time is directly proportional to the number of addresses to be tested. Consider a DI/DO pad 11 that has associated with it m bit lines (or sense amps) (for example, m = 256). 1. Each group of m bit lines (or sense amps) is divided into n (for example, 8) groups of m/n (in this case, 32) bit lines (sense amps). 2. The bit decode is arranged so as to permit: a) One (generally the same location, i.e., 1st, 5th, . .

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RAM Internal Parallel Testing Technique

A RAM (random-access memory) internal parallel testing technique adds circuits to a RAM chip to accomplish test time reduction by testing several addresses in parallel. Significant test time savings are achieved if chips and modules are organized to write and read in several parallel data input/output (DI/DO) channels, reducing the number of addresses that must be tested. To a first approximation, test time is directly proportional to the number of addresses to be tested. Consider a DI/DO pad 11 that has associated with it m bit lines (or sense amps) (for example, m = 256). 1. Each group of m bit lines (or sense amps) is divided into n (for example,
8) groups of m/n (in this case, 32) bit lines (sense amps). 2. The bit decode is arranged so as to permit: a) One (generally the same location, i.e., 1st, 5th, . . ) bit line to be selected in each of the n (8) groups of m/n (32) bit lines. b) Write cycle: upon a command supplied by the tester to a pin of the module (or chip pad) during an otherwise normal write cycle, the following will happen: o All of the appropriate sense amps will begin to set. o The same bit address will be selected in each of the n (8) groups of m/n bit lines. o The signal applied to the tester will disable the 1/n (1/8) bit decode so that the data supplied from the DI/DO pad 11 will be written into the selected bit line of each of the n (8) groups of m/n (32) bit lines. o The write cycle will be terminated normally.

The tester-supplied signal will be removed at...