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CMOS Lssd Shift Register Latch

IP.com Disclosure Number: IPCOM000044673D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Piro, RA: AUTHOR [+2]

Abstract

This article describes a complementary metal oxide semiconductor (CMOS) latch which can be easily implemented in a master slice design without the use of transfer gates, thereby enhancing testability. The diagram shows a two-stage polarity-hold version in which the memory function of the latch is performed by standard CMOS cross-coupled pairs, devices T1 through T4 in the first stage and T13 through T16 in the second. The state of the latch is changed by pulling down either one side or the other. During this transition, one of the pairs of n-channels turns on and overpowers the p-channel pullup of the latch, so as to pull the node down. The output can be taken from either side of the latch and be used to drive a buffer circuit, as shown in the diagram.

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CMOS Lssd Shift Register Latch

This article describes a complementary metal oxide semiconductor (CMOS) latch which can be easily implemented in a master slice design without the use of transfer gates, thereby enhancing testability. The diagram shows a two-stage polarity-hold version in which the memory function of the latch is performed by standard CMOS cross-coupled pairs, devices T1 through T4 in the first stage and T13 through T16 in the second. The state of the latch is changed by pulling down either one side or the other. During this transition, one of the pairs of n-channels turns on and overpowers the p-channel pullup of the latch, so as to pull the node down. The output can be taken from either side of the latch and be used to drive a buffer circuit, as shown in the diagram. Note that the second stage is essentially identical to the first in this design and therefore need not be described separately. Inputs A0, B0 and C0 are clocks, while D0 and I0 are data inputs. The true condition of the data input is used to drive one side of the latch, while the complement drives the other. Thus, during typical operation, when the C0 clock goes high, only one side of the latch can be pulled down. Only one clock input should be asserted at a time. This latch has a number of characteristics which make it well suited for use in a masterslice design. First, the use of only n- channels in the input selectors improves circuit density in an n-well process, where p-channels...