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Techniques for Dynamic RAM Bandwidth Utilization

IP.com Disclosure Number: IPCOM000044676D
Original Publication Date: 1984-Dec-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Bowater, RJ: AUTHOR [+4]

Abstract

This article discloses techniques for the efficient use of the limited bandwidth available for updating a raster scan display dynamic RAM (random-access memory). The RAM has to be updated and refreshed during video flyback so the time available is extremely short. The three techniques combined for efficient storage utilization are: only those memory chips required to be modified have their write enable inputs activated; bit planes are organized in two interleaves of 8 bits each; page mode is associated with 2-way interleave. High resolution raster (frame) buffer display systems usually operate in a 'single buffered' mode where a single RAM store is used for continuous video display, with updating of the store taking place in the video flyback (or blanking times).

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Techniques for Dynamic RAM Bandwidth Utilization

This article discloses techniques for the efficient use of the limited bandwidth available for updating a raster scan display dynamic RAM (random-access memory). The RAM has to be updated and refreshed during video flyback so the time available is extremely short. The three techniques combined for efficient storage utilization are: only those memory chips required to be modified have their write enable inputs activated; bit planes are organized in two interleaves of 8 bits each; page mode is associated with 2-way interleave. High resolution raster (frame) buffer display systems usually operate in a 'single buffered' mode where a single RAM store is used for continuous video display, with updating of the store taking place in the video flyback (or blanking times). Flyback times can be as short as 2 ms for state-of-the-art display monitors. Bearing in mind that a dynamic RAM refresh may have to be performed within this interval, the available time for update cycles may be extremely short. It is therefore extremely important that maximum use is made of this time. The techniques which have been combined to most efficiently use an extremely short time interval are as follows: 1. 'Write Enable Controls' - Typically, raster buffer memories are organized as (for example) 64K words of 16 bits. However, the well-known line generation algorithms (such as Bresenham) may only require to modify one bit in an addressed word leaving all others unchanged. This is usually achieved with a Read-Modify-Write operation involving two memory cycles separated by a data processing cycle in which a complex logic unit modifies (set, reset, exclusive OR etc.) the required bits while leaving all others unchanged. This composite cycle can take up to 500 ns for modern dynamic RAMs. Here, the same effect is achieved by using a 'pulsed write enable' technique in which a single write cycle is performed with only those memory chips required to be modified having their Write Enable signal inputs activated for a very short time (about 75 ns). A word modification cycle therefore r...