Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

High Speed CVS Logic Circuit

IP.com Disclosure Number: IPCOM000044727D
Original Publication Date: 1984-May-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Craig, WJ: AUTHOR

Abstract

The performance of a differential cascode voltage switch (CVS) logic circuit is improved by providing N channel devices 10 and 12 between P channel load devices 14 and 16 and a combinatorial network made of N channel transistors (NMOS). With this serial arrangement stray capacitances in the combinatorial network are not charged to the full supply voltage VH.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

High Speed CVS Logic Circuit

The performance of a differential cascode voltage switch (CVS) logic circuit is improved by providing N channel devices 10 and 12 between P channel load devices 14 and 16 and a combinatorial network made of N channel transistors (NMOS). With this serial arrangement stray capacitances in the combinatorial network are not charged to the full supply voltage VH.

A bias voltage Vbias is applied to the control gates of transistors 10 and 12 which maintains these transistors in an off condition isolating nodes F and F from the NMOS combinatorial network until the voltage on stray capacitor C1 or C2 decreases to a value equal to Vbias minus a threshold voltage VT of transistors 10 and 12. When the voltage on capacitor C1 or C2 equals Vbias-VT, all of the drive through transistor 14 or 16 is applied to charging node F or F.

Disclosed anonymously

1