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Buffered Hard File Attachment

IP.com Disclosure Number: IPCOM000044782D
Original Publication Date: 1984-Aug-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Krishnamurty, R: AUTHOR [+3]

Abstract

This technique reduces the effective speed of a high speed serial storage device such as a hard file to allow the file to be interfaced to a relatively simple, processor-based workstation in an economical manner.

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Buffered Hard File Attachment

This technique reduces the effective speed of a high speed serial storage device such as a hard file to allow the file to be interfaced to a relatively simple, processor-based workstation in an economical manner.

Figure 1 shows the system configuration in the READ mode. Serial CLOCK/DATA is transferred from the hard file to the high speed variable frequency oscillator (VFO) at the rated speed of the hard file. The VFO generates a clock signal, used for data recovery, which tracks the hard file speed. The CLOCK/DATA is assembled into bytes in the 8-bit register and transferred into the random access memory (RAM) buffer. After one or more complete sectors are written into the RAM buffer the CLOCK/DATA is transferred, a byte at a time, from the RAM buffer back into the 8-bit register, and then serially to the low speed floppy disk controller (FDC) at low speed floppy disk rates. This process is under the control of a single chip microprocessor. The microprocessor manages the routing of information on a sector or record basis. The RAM pointer supports byte operations to and from the RAM buffer. The timing element provides critical timing for sector, byte, and bit operations.

In the WRITE mode low speed byte data from the system memory is transferred to the FDC where this data is serialized. Low speed serial CLOCK/DATA from the FDC is transferred to the 8-bit register and then into the RAM buffer a byte at a time. After one or more comple...