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Active Speedup Network for Low Voltage Inverter

IP.com Disclosure Number: IPCOM000044801D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Chang, AY: AUTHOR [+2]

Abstract

The need for a discrete speedup capacitor is eliminated and the saturation of the output pull down device of a conventional low voltage inverter (LVI) is avoided by the use of the active speedup network comprising TC in the drawing.

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Active Speedup Network for Low Voltage Inverter

The need for a discrete speedup capacitor is eliminated and the saturation of the output pull down device of a conventional low voltage inverter (LVI) is avoided by the use of the active speedup network comprising TC in the drawing.

A conventional LVI requires a speedup capacitor connected in parallel with a resistor between the emitter of TO and ground. However, to make a discrete capacitor large enough (approximately 1.0pF) to achieve significant performance improvement requires a large amount of chip area. In addition, since the signal swing, VIN-VOUT, appears across the collector-base junction of TO, it can saturate when VIN is high, VOUT is low and the signal swing is large (>.7V).

Replacing RO and CO, not shown, with a transistor TC eliminates the need for a discrete capacitor and eliminates the saturation of TO .

The operation of the active speedup network is as follows: 1. When VIN is high, VOUT is low and TC is off. Thus there is no path for a saturation current to flow

through TO . 2. As VIN falls from the high level, TEF charges up the

output line capacitance. As VOUT rises, TC passes

through its active region and then moves into heavy

saturation when VIN reaches the low level. 3. When VIN rises from the low level, TO must charge the saturation capacitance of TC, providing overdrive for

TO in discharging the output line capacitance.

Furthermore, if the line stays charged in spite of the

overdrive, TC move...