Browse Prior Art Database

Photoresist Reflow FET Device Process

IP.com Disclosure Number: IPCOM000044805D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Edenfield, A: AUTHOR [+2]

Abstract

A process sequence is disclosed to fabricate a lightly doped drain extension ion implanted FET device.

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Photoresist Reflow FET Device Process

A process sequence is disclosed to fabricate a lightly doped drain extension ion implanted FET device.

Figure 1 shows a first stage in the process where recessed oxide regions 2 formed in the silicon substrate 1 surround a window region 10 wherein the device is to be formed. The thin layer of silicon dioxide 3 is formed on the exposed surface of the silicon substrate 1 in the window 10 and a polycrystalline silicon gate electrode 4 is formed at a central location within the window 10. By using a photoresist blocking mask 5 on top of the polycrystalline silicon electrode 4, the ion implantation of the lightly doped drain extension 6, on either side of the polycrystalline silicon gate electrode 4, can be achieved.

Figure 2 shows a second step in the process sequence, wherein the assembly has been heated so as to reflow the photoresist material 5 so as to assume the shape 5', having sidewalls 7 which cover a portion of the lightly doped drain extensions 6 immediately adjacent to the sides of the polycrystalline silicon gate electrode 4.

Figure 3 illustrates a next step in the sequence, wherein an additional ion implantation step is carried out to form the thicker portions 8 of the source and drains associated with the drain extensions 6, their proximate ends being defined by the respective sides of the sidewall portions 7 of the reflow photoresist 5'.

In this manner, a sufficient thickness can be applied to the source and drains...