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High Speed CMOS NOR Circuit

IP.com Disclosure Number: IPCOM000044806D
Original Publication Date: 1984-Sep-01
Included in the Prior Art Database: 2005-Feb-06
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

An improved speed complementary MOSFET logic circuit is disclosed for carrying out the NOR logical function, by providing a push-pull topology for the circuit.

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High Speed CMOS NOR Circuit

An improved speed complementary MOSFET logic circuit is disclosed for carrying out the NOR logical function, by providing a push-pull topology for the circuit.

The figure shows a two-stage CMOS FET circuit comprising a first stage 1 and a second stage 2. In the first stage 1, P channel FET devices 3 and 4 are serially connected between the node 7 and the voltage VDD, and have the respective binary logic gate inputs A and B. The parallel connected N channel FET devices 5 and 6 are connected between the node 7 and ground potential and have the respective binary value gate inputs A and B. The circuit of stage 1 carries out an elementary NOR logical function, in that when either A or B inputs have a binary one value, the node 7 has a binary zero output value, whereas if the binary values A and B are both zero, the binary output at node 7 is a binary one value.

Node 7 is connected to the gate input of the N channel FET device 8 in stage
2. Stage 2 further includes the serially connected P channel FET devices 9 and 10 which are connected between VDD and the output node 13, devices 9 and 10 being connected in parallel with the N channel FET device 8. N channel FET devices 11 and 12 are connected in parallel between the output node 13 and ground potential. The P channel FET devices 9 and 10 have their gate inputs respectively connected to the binary A and binary B inputs. The N channel FET devices 11 and 12 have their respective inputs connected to the bi...